Responsibilities:

• Perform custom IC layout using Cadence software;
• Duties include cell layout, layout verification, and all similar layout design functions;
• Responsible for layout verification, debugging and layout optimization;

Requirements:

• Diploma or above in Electronics or above with good academic result in circuit theories;
• knowledge in CMOS IC layout;
• knowledge in CMOS device, fabrication process and electronic theories;
• Able to read circuit schematics independently;
• Some basic IC design knowledge would be a plus;
• Some basic knowledge in special analog layout skill such as ESD, Latch-up, matching would be aplus;

Candidate with more experience will be considered as senior or higher grades.

We offer attractive compensation package (5-day work, 10 days annual leaves, medical and dental insurance and Employee Relationship Scheme) to the right candidates. Interested parties please email your full CV with RECENT and EXPECTED salary to our HR Department by clicking "Apply Now" below.

(All personal data collected will be used for recruitment related purpose only).

AppoTech is a fabless semiconductor company, providing a one-stop solution for IC design and application development, and we maintain a series of high-end, mid-range, and low-end products. Based on our application-specific designs, we have developed several application solutions in the areas of Bluetooth, Video, Audio, Wifi, Mobile Storage, MCU for Mobile Power Bank, and home appliances etc.

Our headquarters is in Hong Kong, we also set up operations in mainland China (Shenzhen and Zhuhai) and Taiwan to provide sales and technical support for customers in the Asia Pacific region.

Details can be found at www.appotech.com. We invite you to be a part of the team and bring the company to success, please reach us at [email protected]