Job Responsibilities

Job Purpose

Complete physical layout of analog and digital circuits.  Drawing devices per engineering instructions, running Design Rule Check (DRC) and Layout versus Schematic (LVS) checks, making plots and completing documentation.

Job Description 

• Layout team member who is an active participate in layout design of HV analog products
• Perform layout of HV analog product using Cadence tools
• Perform chip level layout integration. Provide layout plots to design engineer to ensure robustness and compliance to electrical specs
• Layout of test devices and test structures
• Perform verification of layout adherence to design rules, and Layout-vs-Schematic checks

 Job Requirements

• Bachelor of Science in Electronic Engineering or equivalent
• Minimum 5 years of experience in layout of CMOS logic, analog circuits and chip-level products
• Ability to perform top level floor planning
• Hands-on experience on tape-out and stream-out precedure
• Good understanding of matching concepts such as cross-coupled and common-centroid techniques
• Strong understanding and hands on experience using verification tools (Calibre and Hercules) for LVS & DRC
• Good command of English and good communication skills
• Extensive memory/ high voltage/ analog layout experience or knowledge is a plus

Interested parties, please submit your application via our company website: https://microchip.mua.hrdepartment.com/hr/ats/JobSeeker/applyTo/4520

You can also learn more about us at www.microchip.com. 

We will contact shortlisted candidates within 6 weeks. All applications will be strictly confidential and retained for one year for the purpose of staff recruitment only.