The successful candidate will be a member of our Hong Kong design team

Job Responsibilities:

• Work on physical design and integration of IP into SoC
• Floor plan based on area, power and timing constraints
• Perform time-driven Place and Route and Clock tree synthesis
• Perform timing closure and implement fix to meet timing and power budget
• Full chip physical verification (DRC/LVS/EM/IR) and implement fixes to meet requirements
• Generate GDS and data stream out

Job requirements: 

• 5+ years of hands on experience in physical design
• Hands-on experience of Cadence’s EDA tools for physical design implementation in advanced technology
• Experience in hierarchical design, budgeting, multiple voltage domains and multiple clock domains
• Strong expertise in Physical Verification to debug LVS/DRC issues at block level
• Solid understanding of STA and timing constraints
• Experience in managing foundry process / design kit is an advantage
• Knowledge in ESD / Latchup is an advantage

We offer competitive salary packages including 13th month salary and performance bonus. Less experience candidate will be considered as Physical Design Engineer

Interested parties, please apply online through JobsDB "APPLY NOW". Only shortlisted candidates will be contacted. All information collected will be treated in strict confidence and used only for the recruitment purpose.