Responsibilities

• Design from Gate-level netlist to GDSII (include DFT、FloorPlan、 placement、CTS、Routing、Power analysis、SI analysis、STA、Physical verify、XRC);
• Support IC design teams for timing closure;
• Support pre-maskECO & Post-maskECO;
• Support custom analog layout occasionally;

Job requirement

• Bachelor or above in Electronic Engineering;
• 3 years related working experience in semi-conductor industry is preferred;
• Familiar with Encounter or ICC;
• Familiar with EPS (voltusor) redhawk;
• Solid project experience in 55nm or below;
• Familiar with Low power SOC design flow in 55nm or below (eg. UPF、CPF flow);
• Knowledge in timing analysis and optimization;
• Good team working and effective in communication;
• Able to work under pressure and independently;
• Responsible, self-motivated, hardworking, detail-oriented and well-organized;
• Proficiency in spoken and written English and Chinese (include Mandarin);

We offer attractive compensation package according to your academic background and working experience (including 5-day work, medical and dental insurance) to the right candidates. Interested parties please email your full CV with RECENT and EXPECTED salary to HR Department by clicking "ApplY Now" below or visit our website www.appotech.com.

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