Job Responsibilities

• Perform RTL design using the Verilog language and transistor level design using Cadence tools;
• Simulate at the module level and full-chip product level to guarantee data sheet functionality and timing;
• Perform synthesis, static timing analysis at block level and chip level;
• Perform post layout block simulations using SDF back annotation;
• Perform formal verification of RTL vs netlist after synthesis and place and route;
• Interface with and support applications, product, test engineering, marketing, development systems, technology development, CAD, layout and other design organizations;
• Helps validate and debug silicon products to achieve Release to Production;
• Interface and work with global team;

 Job Requirements

• BSEE/MSEE with 0-3 years of experience in IC digital design. MSEE preferred;
• Technical knowledge of IC design methodology;
• Good knowledge of Verilog/System Verilog hardware description language;
• Knowledge of synthesis and static timing analysis;
• Good knowledge of mixed-mode simulation, Cadence AMS;
• Good knowledge of digital circuits;
• Knowledge of analog circuits and circuit simulators is a plus;
• Good knowledge of Unix/Linux based systems as well as scripting languages: Perl and Tcl;
• Knowledge of basic layout concepts and layout software is a plus;
• Good communication skills in writing and speaking English;

Interested parties, please submit your application via our company website:You can also learn more about us at www.microchip.com. 

We will contact shortlisted candidates within 6 weeks. All applications will be strictly confidential and retained for one year for the purpose of staff recruitment only