In May 2008, HiSilicon-Huawei setup an R&D center in Hong Kong, focusing on communication chipset development. Today, we are expanding our R&D work to next generation products that would be used in a wide range of Huawei products. We are looking for enthusiastic and high caliber engineers at all levels to join our team, to support the development from system and architectural design, modeling, micro-architecture design to front-end implementations and verification.

The Senior ASIC Design Engineers will be responsible or take part in defining the micro-architecture of different major functional units of a communication system, focusing on the MAC and physical layer. The individual shall be responsible or contribute to the various phase of the development work, including but not limited to feasibility studies, cost and power estimation, performance and functional modeling, micro-architecture definition, front end design and verification, and synthesis. The individual shall work closely with the rest of the team to deliver the communication SOC that meets the requirements of low cost, low-power, and high performance for wireline networking application.

Responsibilities

ü  Perform architecture, micro-architecture, logic and RTL design using synthesis tools for SOC product.

ü  Verify design by computer simulation and/ or emulation.

ü  Prepare and maintain block diagram, schematics and components information.

ü  Oversee and perform layout design, timing analysis and ECO logic changes.

ü  Evaluate and characterize FPGA/ASIC prototype units.

Desired Skills and Experience

ü  Minimum of 3 years of proven design or verification experience in complex SOC projects

ü  Experience with CPU/ASIC architecture/design/verification

ü  Experience with the design/verification in one or more of the following disciplines

• Computer Vision Algorithms/Scheme, e.g. Pixel Transfoms, Compositing and Matting, H.264, MPEG4, JPEG, etc
• Network and High Speed Interfaces, e.g. XGMII, RGMII, GMII, SERDES
• SOC processor and peripherals, e.g. ARM cores, DSP cores, SPI, UART, GPIO etc.
• DSP Algorithms, e.g. Digital Filters, FFT etc.

ü    Knowledge of simulation and synthesis tools on FPGA/ASIC

ü    Must be a highly organized, detail-oriented self-starter, who works well independently, as well as in a team environment

ü  BS or higher degree in Electrical/Computer Engineering.

ü  Good verbal and written communication skills

ü  Candidates with less experience will be considered as ASIC Design Engineer.

We offer competitive remuneration package to the right candidate. Interested parties please send your full resume with present and expected salary, available date. All information collected is strictly for recruitment purpose.