Job Responsibilities:

• Perform logic synthesis, DFT, static timing analysis, place & route, library characterization
• Support ATPG and functional test program development, test coverage analysis
• Support other physical design and verification tasks
• Support wafer level testing and silicon evaluation

Job Requirements:

• Bachelor Desgree or above in Electronic Engineering or equivalent
• 5 years or above solid experience in digital implementation flow
• Proven track record of implementing design through synthesis, floor-planning, place & route, extraction, timing, and physical verification
• Strong understanding of constraints generation, STA, timing optimization, and timing/SI closure
• Experience with multi-power domain designs
• Knowledge of IR/EM closure
• Strong scripting skills toward flow customization and efficiency
• Candidate with less experience will be considered as Digital Design Engineer