• Responsible for schematics and layout design of digital, RF, analog, mixed signal, or power IC, including all facets of the design flow, from schematics to layout, from initial floor-planning to final verification
• Develop algorithms, building blocks, firmwares, SoC, or testing solutions for various smart city and industry 4.0 related applications
• Work with marketing and technology transfer team to prepare engineering prototypes and conduct on-site tests

• Degree holders (Bachelor/Master/Ph.D.) in Electronic Engineering or related fields with minimum of 3 years related experience
• Extensive experiences in digital, RF, analog, mixed signal, or power IC design
• Familiar with EDA Tools (e.g., Cadence/ Mentor/ Synopsys). Rich programming knowledge such as C/C++, Python, Matlab, Verilog, Skill, or TCL is preferred
• Good communication and interpersonal skills, a good team player
• Proficiency in written and spoken English
• Overseas candidates are welcomed to apply. For the right candidate, the company can sponsor an Employment Visa in Hong Kong
• Lives ASTRI values

Application

The appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work a five-day week.

Interested candidates, please send an application (quoting Ref. No.) with a detailed resume, current and expected salary to Talent Acquisition via email. The resume should not include any sensitive personal information such as HKID or passport number, photo, etc.

Position offer is subject to the applicant’s experience and academic qualification. The application will be open until the position is filled. Only short-listed candidates will be notified. ASTRI reserves the right not to fill the position.

ASTRI is an Equal Opportunities Employer. Personal data provided by job applicants will be used exclusively for recruitment only. For details, please refer to ASTRI Privacy Policy Statement., in particular section 9.